Statistical Thermal- and Timing-Constrained Circuit Optimization
碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of ower consumption and integration density has led to high operating temperature. Temperature...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/28879910534453839248 |