Impacts of Process Variables on Local Strained MOSFETs

• Main Authors: Chung-Shen Cheng, 程仲陞
• Other Authors: Chen-Hsin Lien
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/27618302601852206947

碩士 === 國立清華大學 === 電子工程研究所 === 94 === In this thesis, we simulated the local strained channel PMOS & NMOS by stress control techniques. Heavy mechanical stress was produced by deposition of a tensile SiN-capping layer after all the traditional device processes of NMOS, which results in the improvement of the electron mobility. For PMOS, the epitaxial SiGe source/drain produced compressive stress in the channel region and improves the hole mobility. We discussed the impacts of variable changes of the manufacturing process on the device, including the thickness of SiN-capping layer, wafer orientation, channel direction, S/D thickness, and the gate oxide material. Thicker nitride layer improves NMOS with a limit of 180nm but degrades PMOS. Stress hardly changes in different wafer orientation and channel direction, but piezoresistive effect influences most for NMOS with (100) substrate /channel and for PMOS with (110) substrate /channel. For NMOS, thicker NiSi S/D induces more tensile stress in the channel and more compressive stress in the out-of-plane direction. For PMOS, thicker SiGe S/D induces more compressive stress in the channel and more tensile stress in the out-of-plane direction with a limit of 60nm. As far as stress is concerned, SiO2 is the better gate dielectric than SiON.