Enabling Software Pipelining for PAC VLIW DSP Processors
碩士 === 國立清華大學 === 資訊工程學系 === 94 === Software pipelining is a powerful loop optimization technologyi in compiler. It overlaps the execution of adjacent loop iterations to improve performance. However it has to consider many constraints in the scheduling phase to achieve this purpose. Many miscellaneo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15417222746809905644 |