Probabilistic Approach for Logic Equivalence Checking
碩士 === 國立清華大學 === 資訊工程學系 === 94 === Logic equivalence checking plays an important role in VLSI design flow. Recently, the effort of logic equivalence checking occupies 60%~80% effort of the whole design flow. Hence, an efficient algorithm for logic equivalence checking is needed and probabilistic ve...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/37094057086494630820 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 94 === Logic equivalence checking plays an important role in VLSI design flow. Recently, the effort of logic equivalence checking occupies 60%~80% effort of the whole design flow. Hence, an efficient algorithm for logic equivalence checking is needed and probabilistic verification is proposed. Probability expressions of circuits are built and compared. Recently, replacing primary inputs into real numbers is used. In [8], a perfect input assignment for probabilistic verification is proposed and this approach does not cause aliasing. But this input assignment approach needs plenty of calculation and memory usage while the input number is huge. Hence, we propose an advanced approach to reduce the usage of input assignments. We check internal equivalent gates of circuits and replace them with a single assignment. Experimental results show that our approach is workable in practical circuits.
|
|---|