Probabilistic Approach for Logic Equivalence Checking
碩士 === 國立清華大學 === 資訊工程學系 === 94 === Logic equivalence checking plays an important role in VLSI design flow. Recently, the effort of logic equivalence checking occupies 60%~80% effort of the whole design flow. Hence, an efficient algorithm for logic equivalence checking is needed and probabilistic ve...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/37094057086494630820 |