| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 94 === The clock skew issue is getting more serious in high-speed high-density systems. While PLL/DLL are applied to compensation of clock skew, they require more than hundred clock cycles to lock in, this not only makes power management inefficient, but also makes date rate decreased. Although conventional synchronous mirror delay takes only two clock cycles to lock in, it consists of one or several long delay lines. Therefore, the area overhead and standby current will be a critical issue in the system of multiple-clock or high-performance power management. Especially, they are more serious on multi-core system.
In this thesis, we propose a congruence synchronous mirror delay based on the congruence theorem and the concept of ring-counter in order to improve the conventional synchronous mirror delay or mirror-type synchronous circuits to reach the demands of low-power, high-speed and low-area. In general applications, our design can save the area more than 60%. As for the measurement of static phase error, a Vernier delayline is developed, and a mean statistical static phase error within 75.7ps~120ps is obtained. Finally, the simulation and layout are completed by using a 0.35um 2P4M technology. The operation frequency is between 72MHZ~454MHZ and the core size of chip is 230.5um*105.7um excluding measurement circuit and I/O Pad.
|
|---|
