Congruence Synchronous Mirror Delay and its Built-In Self Test
碩士 === 國立彰化師範大學 === 電子工程學系 === 94 === The clock skew issue is getting more serious in high-speed high-density systems. While PLL/DLL are applied to compensation of clock skew, they require more than hundred clock cycles to lock in, this not only makes power management inefficient, but also makes dat...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31190844716031783795 |