A High-Resolution Arbitrary Duty-Cycle Synchronous Mirror Delay Circuit
碩士 === 國立中央大學 === 電機工程研究所 === 94 === With the evolution of CMOS process technology, the clock synchronization becomes truly an important issue. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems in order to suppress the clock skew. There a...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/3x27e9 |