Design of Multi-Core Embedded Processor Using Configurable Master-Slave I-Cache Controller

• Main Authors: Ching-Hsiang Chou, 周經翔
• Other Authors: Chin-Teng Lin
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/66706797394891330274

碩士 === 國立交通大學 === 電機與控制工程系所 === 94 === Cache miss is a very significant factor to affect its efficiency for the General Embedded Processor in general applications or the Digital Signal Processor(DSP) emphasizing on computing operations. The cache miss results in the penalty of wasting of thousands of cycles or more. For this reason, if we design a cache controller that can reduce the number of cache miss and save miss penalty, we will enhance the efficiency of the processor. In the paper, an I-Cache controller hardware algorithm that can be applied in Chip is introduced. When this algorithm is applied for general application program, it can efficiently reduce the total miss penalty of the I-Cache. Even more, we can see the significant effect when it is applied for the multi-media application that has many loop operations and function calls. In order to prove the dependability and the correctness of the algorithm, the thesis designs a multi-core embedded processor that has VLIW architecture. That can be used for the operation platform of the I-Cache controller, and be intergraded into a embedded processor chip. This Chip is fabricated in UMC 0.18μm process and designed in the way of Cell-based. The chip area is 3.1x3.1 mm2 , and the max operation frequency is operated at 135MHz.