Design of Multi-Core Embedded Processor Using Configurable Master-Slave I-Cache Controller
碩士 === 國立交通大學 === 電機與控制工程系所 === 94 === Cache miss is a very significant factor to affect its efficiency for the General Embedded Processor in general applications or the Digital Signal Processor(DSP) emphasizing on computing operations. The cache miss results in the penalty of wasting of thousands o...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66706797394891330274 |