Study on Reliability of Low-Temperature Polycrystalline Silicon Thin Film Transistors under Dynamic Stress

• Main Author: 李逸哲
• Other Authors: Po-Tsun Liu
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/03068525068253463206

碩士 === 國立交通大學 === 光電工程系所 === 94 === The low temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) have become the main technology and are applied for active matrix liquid crystal display (AMLCD), organic light emitting diode, and driving circuits. Recently, the low temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) with high field-effect mobility and high driving current can be fabricated by several novel crystallization technologies. However, the main grain boundaries different from the general grain boundaries made by solid phase crystallization (SPC) are generated in the channel due to these novel technologies. The main grain boundaries play an important role of the degradation of the devices under dynamic operation. The low temperature polycrystalline (poly-Si) thin film transistors (TFTs) are operated under gate bias alternative current signal and subjected to electrical stress while it is applied for driving circuits. Thus, the study of influence of grain boundaries on reliability of low-temperature polycrystalline silicon thin film transistors under dynamic gate bias stress becomes important. In this thesis, we adopt the low temperature polycrystalline silicon thin film transistors fabricated by the excimer laser annealing and the novel process for the instability research. In addition, the capacitance-voltage analysis was employed to study on the degradation of excimer laser annealing low temperature polycrystalline silicon thin film transistors under dynamic stress. We also used current-voltage analysis to investigate on the degradation of thin film transistors fabricated by novel process under dynamic stress. In capacitance-voltage analysis, the applied small signal does not affect the fixed oxide charge. However, the traps at different states were responded to different measurement frequency due to different depth of states. Deeper trap states need longer emission time corresponding to larger measurement frequency; shallow trap states need shorter emission time corresponding to smaller measurement frequency. Therefore, we used not only different measurement frequency, 10 KHz, 100 KHz, 1 MHz, but also different stress time, 10 s, 100 s, 1000 s, to investigate the degradation of trap density of state of low temperature polycrystalline silicon thin film transistors. In current-voltage analysis, we also studied on the novel process thin film transistors whose main grain boundary may exist in the channel. After dynamic stress, not only excimer laser annealing but also novel process thin film transistors without lightly doped drain were degraded more severe than ones with lightly doped drain, that exhibits on rapid degradation of on-current and mobility. Furthermore, the geometry of the novel process fabricated thin film transistors is prominent at the polycrystalline silicon and gate oxide interface. Since the shape of the main grain boundary is unusual, the electric field at the main grain boundary is concentrated on gate oxide interface. Therefore, the region is subjected more stress under dynamic stress. The polycrystalline silicon thin film transistors with main grain boundary in the channel (GB) were degraded more than that without main grain boundary in the channel (NGB).