Design of Pulsewidth Control Loop with a Built-In Delay-Lock Loop
碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === In system chip, PLL and DLL are mostly used to generate the clock for different sub-circuits in the system. Therefore, the quality of clock signals will influence the efficiency of the entire system. This thesis introduces a pulsewidth control loop with a built-...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68670442511860914278 |