Reconfigurable Scan Chain Design for Delay Fault Testing
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === Enhancing coverage for delay fault testing has becoming more important for deep sub-micron designs. The general method in delay fault testing is by scan-based approach. Although the fault coverage of general circuits can be up to at least 60~70 percent, ther...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49251464621904773593 |