FPGA based a realization of BCH step-by-step decoding
碩士 === 大葉大學 === 電信工程學系碩士班 === 94 === In general, an algebraic decoder is with high hardware complexity or a conventional step-by-step decoder is with long decoding delay, and both of them are not efficient for a cyclic code in terms of decoding complexity. In order to overcome this difficulty, a mod...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/50936397035222526195 |