A 622Mb/s Clock and Data Recovery for OC-12 SONET Applications
碩士 === 中原大學 === 電子工程研究所 === 94 === The goal of this thesis is to design a 622Mb/s Clock and Data Recovery (CDR) Circuit for SONET OC-12 optical networks. The CDR circuit is based on the structure of Phase Locked Loop (PLL).And, The function of the CDR circuit is to recover the clock information whic...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49784061129760082288 |