Array Structure Recognition in Flatten Layout
碩士 === 元智大學 === 資訊工程學系 === 93 === This thesis proposes an algorithm to find out array structures from a layout design. The so-obtained array structures can be employed to reduce DRC processing time. Our algorithm consists of five phases. In the first phase, we build a R-B tree for all the cells with...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25748222726432973482 |