High Speed and Energy Efficient 10-Transistor Full Adder Design

• Main Authors: Cheng-che Ho, 何政哲
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/47514434326546544285

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === How to handle the balance of the performance and power consumption in layout area reduced design is the most important issue for designer. In this paper, we proposed a novel full adder design featuring both low voltage and low energy ( power delay product ) operation using as few as 10 transistors per bit. To achieve low voltage operation, the design adopts inverter based XOR/XNOR designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from direct cascading if no extra buffering is employed. The proposed design successfully embeds the buffering circuit in the full adder design so that the transistor count is kept as minimum. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both DC and AC performances of the proposed design are evaluated against various full adder designs via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35μm process models, indicate that the proposed design has the lowest working Vdd ( 1.9V ) and highest working frequency ( 1300MHz @ 3.3V ) among all designs using 10 transistors. It also features the highest frequency and lowest energy consumption per addition in the application of ripple carry adder.