High Speed and Energy Efficient 10-Transistor Full Adder Design
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === How to handle the balance of the performance and power consumption in layout area reduced design is the most important issue for designer. In this paper, we proposed a novel full adder design featuring both low voltage and low energy ( power delay product )...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47514434326546544285 |