The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop

The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector chara...

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Main Authors: Ming-yu Hsieh, 謝明育
Other Authors: Roger Yubtzuan Chen
Format: Others
Language:zh-TW
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/04449727833180375713
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spelling ndltd-TW-093YUNT53930172015-10-13T11:54:00Z http://ndltd.ncl.edu.tw/handle/04449727833180375713 The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop 寬頻低功率鎖相迴路設計與製作 Ming-yu Hsieh 謝明育 碩士 國立雲林科技大學 電子與資訊工程研究所 93 A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector characteristics and a high frequency-sensitivity. A full-switching low-noise differential delay cell is designed and employed to implement the differential range-programmable ring oscillator. Dual-delay path scheme is employed and leads to higher and wider output frequency range. A wide output-frequency range, from 85MHz to 1.36GHz, is achieved from the VCO in a power-efficient manner. The differential range-programmable ring oscillator shows substantial improvement in its output jitters, according to our jitter simulation in the presence of supply noise. Roger Yubtzuan Chen 陳育鑚 2005 學位論文 ; thesis 73 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector characteristics and a high frequency-sensitivity. A full-switching low-noise differential delay cell is designed and employed to implement the differential range-programmable ring oscillator. Dual-delay path scheme is employed and leads to higher and wider output frequency range. A wide output-frequency range, from 85MHz to 1.36GHz, is achieved from the VCO in a power-efficient manner. The differential range-programmable ring oscillator shows substantial improvement in its output jitters, according to our jitter simulation in the presence of supply noise.
author2 Roger Yubtzuan Chen
author_facet Roger Yubtzuan Chen
Ming-yu Hsieh
謝明育
author Ming-yu Hsieh
謝明育
spellingShingle Ming-yu Hsieh
謝明育
The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
author_sort Ming-yu Hsieh
title The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
title_short The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
title_full The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
title_fullStr The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
title_full_unstemmed The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
title_sort design and implementation of a wide-range power-efficient cmos phase locked loop
publishDate 2005
url http://ndltd.ncl.edu.tw/handle/04449727833180375713
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