The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector chara...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04449727833180375713 |