The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector chara...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/04449727833180375713 |
| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector characteristics and a high frequency-sensitivity. A full-switching low-noise differential delay cell is designed and employed to implement the differential range-programmable ring oscillator. Dual-delay path scheme is employed and leads to higher and wider output frequency range. A wide output-frequency range, from 85MHz to 1.36GHz, is achieved from the VCO in a power-efficient manner. The differential range-programmable ring oscillator shows substantial improvement in its output jitters, according to our jitter simulation in the presence of supply noise.
|
|---|