Design Techniques for Low-Power High-Speed CMOS Sample-and-holdCircuit with Low Hold Pedestal
博士 === 國立雲林科技大學 === 工程科技研究所博士班 === 93 === Low-power design of high-speed analog to digital converters (ADCs) is a major objective in many applications such as battery-powered portable video devices. However, sample-and-hold (S/H) circuits play an important role in the design of data-converter system...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/17063732850035269273 |