Design and Implementation of VLSI Cell Library for Self-timed Systems

• Main Authors: Chih-Wen Yang, 楊智文
• Other Authors: Fu-Chiung Cheng
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/35571945905533954741

碩士 === 大同大學 === 資訊工程學系(所) === 93 === Asynchronous circuits have potentially the advantage of low-power consumption, modularity and high-performance. It is necessary to have self-timed cell library to implement asynchronous VLSI chips in current asynchronous design flows. This thesis presents the design and implementation of a self-timed VLSI cell library to facilitate automatic system-level synthesis. From the results of our experiment, it is correct that we simulate and verify the circuits when synthesizing asynchronous circuits with TSMC standard cell library during pre-layout simulation. But we get incorrect output values when we simulate and verify the circuits in post-layout simulation. When we use our self-timed cell library to synthesize asynchronous circuits, we get correct results. But in pre-layout simulation the area will increase 3% and the speed will increase 10% in comparison with TSMC standard cell library. On the other hand, TSMC provides standard cells such as AND, OR, NOT and XOR, which area and speed are better than our designing standard cells. Therefore, we synthesize asynchronous circuits with our self-timed cells, such as C-element, Toggle, and TSMC standard cells. In pre-layout simulation the area reduces 14% and the speed improves 20% in comparison with TSMC standard cell library.