Design and Implementation of VLSI Cell Library for Self-timed Systems
碩士 === 大同大學 === 資訊工程學系(所) === 93 === Asynchronous circuits have potentially the advantage of low-power consumption, modularity and high-performance. It is necessary to have self-timed cell library to implement asynchronous VLSI chips in current asynchronous design flows. This thesis presents the des...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35571945905533954741 |