A New Architecture Design for Data Phase-Locked Loops and Frequency Synthesizers without Dead-Zone Effects
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 93 === In this thesis, we propose a new architecture used in data phase-locked loops and frequency synthesizers. Some characteristics will be improved when we use the proposed architecture. We proposed the data phase-locked loop which has system simple, smaller cap...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83rxfn |