Analysis of Capacitance Behavior in SOI CMOS Devices Using 2D and 3D Simulation

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD...

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Bibliographic Details
Main Authors: Guei-Syuan Lin, 林桂萱
Other Authors: 郭正邦
Format: Others
Language:zh-TW
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/55730048886135081714
Description
Summary:碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.1μm, the source sidewall fringing capacitance(CFSS) is the most important contribution to the gate-source capacitance (CGS) as compared to the inner oxide fringing capacitance (CFIS)and the drain side fringing capacitance (CFDS). For the gate-drain capacitance (CGD), the drain sidewall fringing capacitance (C’FDS) is the most important. In chapter 3, this thesis reports the floating-body kink-effect related capacitance behavior of nanometer PD SOI NMOS devices. From the 2D simulation results, at the onset of the DC kink effect, there are sudden jumps in the CSG/CDG curves due to the excess holes stored in the thin-film as a result of the turn-on of the bipolar device.