Analysis of Capacitance Behavior in SOI CMOS Devices Using 2D and 3D Simulation
碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55730048886135081714 |