| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 93 === Recently embedded memories are the most widely used cores in system-on-chip (SOC). They often occupy most of the chip area and dominate the overall yield of the chip. For the sake of improving the manufacturing yield of the chip, memory Built-In Self-Repair (BISR) has become essential. Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of an address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves a significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. During memory access, read operations to the main memory and spare memory are executed in parallel. However, the write operation to spare memory is divided into two steps. Data is first written into the write buffer, then into the spare memory when the next write operation arrives. Therefore, there is one clock cycle to compare the access address with the address stored in the repair registers. With the proposed address remapping scheme and the redundancy architecture, the timing penalty of our BISR scheme is the same with that of Built-In Self-Test (BIST) circuit — only one multiplexer delay for both the inputs and outputs.
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