An Enhanced SRAM BISR Design with Reduced Timing Penalty
碩士 === 國立清華大學 === 電機工程學系 === 93 === Recently embedded memories are the most widely used cores in system-on-chip (SOC). They often occupy most of the chip area and dominate the overall yield of the chip. For the sake of improving the manufacturing yield of the chip, memory Built-In Self-Repair (BISR)...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14943690316830321582 |