| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 93 === The foundry provides not only the design rules but also resistances and capacitances of the mainstream test structures of interconnect for designers in the process of the back-end of line of VLSI. These capacitances and resistances affect the design of circuits and yield, so the accuracy of RC extraction is very important. Accurately simulating the capacitances and resistances of interconnect will add the yield of chips. During the process of the dry etch, there will be the microloading effect because of different etch rate. In early age, the dielectric layers with high dielectric constant (High-K) are used to avoid the effect, which are known as etch stop layers. Because the technology of process grows up and the requirement of the performance of the chips increases, RC delay is more important. In order to reduce RC delay, decreasing the use of the dielectric layers with high constant becomes a trend in the modern process. Thus, the dimensions of metal lines will be affected by microloading effect. This paper focuses on the impact of microloading effect to the capacitance of interconnect. And there is simulation on how the dimensions of metal lines change under microloading effect and capacitance extraction based on the dimension simulation just mentioned. Beside, it compares these capacitances with the capacitance without microloading effect to understand the difference between them. It becomes greater than 10% in many cases. There are several important cases where around 30% to 50% are observed. In brief, the paper lets us to know that it is necessary to consider the microloading effect, if we want to simulate the capacitances of interconnect more accurately in the modern process.
|
|---|
