| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 93 === With the rising complexity of designs, design verification has become a bottleneck of the VLSI design process. Among techniques of design verification, random simulation verification has attracted much more interests due to its ability of both automatically generating large verification vectors and uncovering obscure bugs. However, random vector generator may produce input vectors which are “illegal” to a circuit’s inputs. As a result, designers are required to provide the constraint equations to prevent generating of illegal input vectors.
The exact constraint equations are very difficult to derive and error-prone. In this thesis, we propose a hardware model called Constraint Hardware Model, which can avoid generating illegal input vectors. The Constraint Hardware Model can be automatically translated from design environment without the need of writing constraint. We conducted experiments on several combinational benchmark circuits. The experimental results show that our approach can shrinks the circuit size to 10% of the benchmark circuits and reduces the number of primary inputs to 29% of the benchmark circuits.
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