Constraint Hardware Model for Efficient Random Verification
碩士 === 國立清華大學 === 資訊工程學系 === 93 === With the rising complexity of designs, design verification has become a bottleneck of the VLSI design process. Among techniques of design verification, random simulation verification has attracted much more interests due to its ability of both automatically genera...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94749340202489707343 |