Simple Yet Effective Algorithms for Block and I/O Buffer Placement in Flip-Chip Design

• Main Authors: Hao-Yueh Hsieh, 謝皓岳
• Other Authors: Ting-Chi Wang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/55906060241086552224

碩士 === 國立清華大學 === 資訊工程學系 === 93 === Flip-chip bonding was developed by IBM in 1964. Flip-chip bonding facilitates higher I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high performance digital systems. In this thesis, we study the problem of block and I/O buffer placement in flip-chip design. The goal of the problem is to simultaneously minimize the total path delay and the total skew of all input/output signals. We present two simple yet effective algorithms for the problem. Both algorithms place blocks to minimize the total path delay, and place I/O buffers to minimize the total path skew. As compared to an existing method [5], the experimental results show that both algorithms are able to get placement solutions of smaller weighted costs of total path delay and total path skew with the improvement rates up to 65% and 77.5%, respectively, and to run much faster. Moreover, when the second algorithm is modified to consider rotations of blocks and I/O buffers as well, the improvement rate becomes even higher, up to 82.4%. Finally, we extend our second algorithm to solve the bounded skew problem where the skew becomes a constraint to satisfy (instead of a part of the cost function to be minimized). The experimental results show that the total path delay could be further reduced by up to 32.8% and 40% without and with considering rotations of blocks and I/O buffers, respectively.