| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 93 === Delay variation can cause a design to fail its timing specification. Research [5, 12] observes that the worst case of a design is highly improbable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their xperimental results show significant performance or power gain as compared to the worst-case design. However, the architecture in [5, 12] suffers the short path problem which is difficult to resolve in the advanced technology. In this thesis, we propose a Timing Error Detection (TED) architecture without using a delayed clock and therefore the TED architecture is free from the short path problem. Given a design and a maximum delay margin, our algorithm
can automatically construct a TED architecture to tolerate the given delay margin. Our experimental results also show that the TED architecture can be a good alternative for those cases where the minimum delay is difficult to
meet in the advanced technology.
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