Synthesis of a Novel Timing Error Detection Architecture
碩士 === 國立清華大學 === 資訊工程學系 === 93 === Delay variation can cause a design to fail its timing specification. Research [5, 12] observes that the worst case of a design is highly improbable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54749626504975597989 |