Design of a Basic Block Reassembling Instruction Stream Buffer for X86 ISA
碩士 === 國立中山大學 === 電機工程學系研究所 === 93 === Nowadays, X86 CPU all have superscalar computing ability. Superscalar architecture can fetch, execute and commit more than one instruction per cycle. And it helps a lot to explore more instruction level parallelism. If a superscalar processor fetches instructio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00317071996137286871 |