| Summary: | 碩士 === 國立彰化師範大學 === 電機工程學系 === 93 === This thesis proposes a multiple frequency channel selector based delay-locked loop frequency synthesizer designed in 0.18-μm CMOS process with 1.8V supply voltage. DLL has several inherent advantages over the PLL, i.e., no jitter accumulation, fast locking, stable loop operation and easy integration of the loop filter. This proposed architecture uses a multiple frequency channel selector to down convert the RF receiver signal. In order to obtain twelve frequency channels, we design a novel multiple frequency circuit for WCDMA application. The novel multiple frequency circuit can generate N multiple frequency. In addition, we improve the other circuits to increase the whole efficiency. These circuits include waveform converter, buffer circuit, and voltage-controlled delay line. The waveform converter transforms a square wave signal to produce in-phase and quadrature-phase sinusoidal signal outputs. The multiple frequency channels are generated from 422MHz to 434MHz. The frequency multiplication of waveform converter is set five in the structure, and the output receiver frequency operates from 2.11GHz to 2.17GHz. The bandwidth of channel is 5MHz. When the output frequency is 2.11GHz, the phase noise at 100kHz offset from the carrier is –128dBc/Hz, and the power consumption is 5.8mW with 350ns locked time.
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