A Delay-Locked Loop Frequency Synthesizer for WCDMA Applications
碩士 === 國立彰化師範大學 === 電機工程學系 === 93 === This thesis proposes a multiple frequency channel selector based delay-locked loop frequency synthesizer designed in 0.18-μm CMOS process with 1.8V supply voltage. DLL has several inherent advantages over the PLL, i.e., no jitter accumulation, fast locking, stab...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67213742631769414672 |