Algorithms for Connectivity Verification of Random Access Memories
碩士 === 國立中央大學 === 電機工程研究所 === 93 === Abstract A large memory is typically designed with multiple identical memory blocks for reducing access time and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However,...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67797412455589789397 |