Design and Analysis of Multiphase DLL-based Frequency Multipliers
碩士 === 國立中央大學 === 電機工程研究所 === 93 === Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as local oscillator and clock generator where only used with PLL in the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59890805564531279758 |