Automatic Assertion Checking Using Formal Symbolic Model Verifier
碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 93 === Assertion based verification (ABV) methodology has emerged as a paradigm of high-level design verification. An assertion is used to specify what is to be exercised and verified against the intended functionality. However assertions which may contain conflict...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15654269991971750495 |