A Modeling and Verification Platform for Communication SoC Designs
碩士 === 國立交通大學 === 電子工程系所 === 93 === This thesis introduces a development and verification platform that combines hardware modeling and communication system simulation. The hardware modeling is an important technology in SoC design process, and system simulation is an essential process in communicati...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83120522494499157799 |