Built-in Self Test for jitter measurement
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === Phase-locked loops (PLLs) are often served as clock generators and/or frequency synthesizers in a system on a chip (SoC). Since it is usually built inside the chip deeply, it is hard to test PLL directly by using automatic test equipments (ATEs). For a clock...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30296290427134359925 |