A 10-bit 500M-sample/sec Digital to Analog Converter

• Main Authors: Kuan-Hung Chou, 周冠宏
• Other Authors: Ching-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/82184302127011166824

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === 　In this paper, a 10-bit 500-MSample/s CMOS digital-to-analog (D/A) converter is presented. It is based on a current steering segmented 5 + 5 architecture that comprises 5MSB’s unary cells and 5LSB’s binary weighted cells in this design. 　The 500-MSample/s conversion rate has been obtained by an, at transistor level, fully custom designed thermometer decoder and synchronization circuit. In the digital part, a high speed, high output crossing-point latch is designed to minimize the glitch energy. Moreover, using cascade current cell in analog part can increase the output impedance and improve the performance of the SNDR and SFDR. 　From the simulation result, the glitch energy is 0.995 psec-V. For a near 250 MHz input signal at 500 MHz sampling rate, the SNDR is about 60dB. The power consumption of this DAC with a single 3.3V supply is 70 mW. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. This DAC chip is fabricated using TSMC 0.18μm-1P6M CMOS process and the die area is 1.07mm×1.07mm.