A 10-bit 500M-sample/sec Digital to Analog Converter
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === In this paper, a 10-bit 500-MSample/s CMOS digital-to-analog (D/A) converter is presented. It is based on a current steering segmented 5 + 5 architecture that comprises 5MSB’s unary cells and 5LSB’s binary weighted cells in this design. The 500-MSample/s con...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82184302127011166824 |