| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 93 === The modified Booth fixed-width multiplier receives n-bit input and produces n-bit output. This thesis proposes an error compensation method for a fixed-width multiplier that uses modified Booth algorithm. The truncated part is divided into 2 parts, LPmajor and LPminor. For the reason that LPmajor has dominant effect on the sum of retained cells, S_MP, the sum of LPmajor is computed exactly. The sum of LPminor is computed approximately since it has little contribution on S_MP. Using Karnaugh-map to generate the compensation bias is the first proposed method in this thesis, then another improvement is proposed since it’s time-consuming to draw the K-map from a multiplication of large numbers. The multiplier input values are first classified into several groups and each group is associated with a different compensation bias, which is computed directly from Booth encoder outputs rather than multiplier coefficients. By simulations, the proposed design performs about 2 dB higher PSNR than the existing method. That is, the MSE is reduced up to 1.1832 compared with the state-of-art designs. It saves up to 15% area compared with modified Booth multiplier without truncating any cell.
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