Design of Low-Error Fixed-Width Multiplier for Convolution Computations
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 93 === The modified Booth fixed-width multiplier receives n-bit input and produces n-bit output. This thesis proposes an error compensation method for a fixed-width multiplier that uses modified Booth algorithm. The truncated part is divided into 2 parts, LPmajor an...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39634452284527294877 |