Low Power Bus Coding Architecture for System-on-Chip Data and Address Busses

• Main Authors: Chia-Hao Fang, 方嘉豪
• Other Authors: Chih-Peng Fan
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/76817103836185384520

碩士 === 國立中興大學 === 電機工程學系 === 93 === In modern VLSI design, low power design is one of the key issues. Since on-chip and off-chip bus consume a general quantity of power, one of the effective methods to reduce the power consumption on chip is to reduce the power consumed by the on-chip and off-chip buses. Therefore, bus coding methods, that make capital of bus value characteristics to reduce the switching activity and static current loss on a bus, have been proposed to accomplish the objective. In integrated circuit, major sources for power dissipation include load capacitance, switching activity, work frequency and supply voltage. Based on the above power dissipation factors, every engineer has to solve power dissipation question in different design levels, including circuit level, architecture level, and gate level. The power dissipation, in the main, is in proportion to load capacitance. Moreover, the load capacitance from off-chip buses is about thousands of that from on-chip buses. Relatively, the power dissipation from off-chip buses is about thousands of that from on-chip buses. If we are effectively lowered the switching activity of the bus, we can reduce power dissipation significantly. In this thesis, the purpose of the proposed new coding technique is to effectively diminish the switching activity on the busses. In addition, it can save dynamic power consumption. The proposed encoding method is called the XOR-BITS code. The XOR-BITS coding can be used on address bus and it can also be applied on data bus simultaneously. It can reduce about 74% switching activity in the address bus. Meanwhile, it can also reduce switching activity in the data bus for about 14%. Consequently, the proposed XOR-BITS code can not only save more power consumption but also extend the whole system working time. Our bus coding method contrasts mutually with other bus coding method. The XOR-BITS coding is verified to achieve less switching activity than other coding methods on data bus and address bus. Besides, the increase of the circuit complexity is limited. We have used the MATLAB© software to calculate the switching activities in behavior simulation. Furthermore, we have used the Design Vision© software to synthesize our bus coder, and estimate the gate counts and power consumption.