Low Power Bus Coding Architecture for System-on-Chip Data and Address Busses
碩士 === 國立中興大學 === 電機工程學系 === 93 === In modern VLSI design, low power design is one of the key issues. Since on-chip and off-chip bus consume a general quantity of power, one of the effective methods to reduce the power consumption on chip is to reduce the power consumed by the on-chip and off-chip b...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76817103836185384520 |