Design and Implementation of a Scalable High-Performance AES Cipher Chip
碩士 === 輔仁大學 === 電子工程學系 === 93 === A scalable high-performance AES cipher processor is proposed in this thesis. Since the design and implementation of the S-Box is the critical step for implementing the entire AES encipher/decipher, a modularized methodology is adopted to implement it. According to t...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/hqh7g6 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 93 === A scalable high-performance AES cipher processor is proposed in this thesis. Since the design and implementation of the S-Box is the critical step for implementing the entire AES encipher/decipher, a modularized methodology is adopted to implement it. According to the algorithm of the S-box, two types of basic modules can be derived. These two types of basic modules can be combined to form three types of S-box. The user can select among these types according to performance and area specifications. In order to verify our approach, an AES-128 processor is implemented with 0.18 m 1P6M CMOS technology. The gate count is 38.5 K. The operating frequency is 275 MHz and the throughput is 457 Mb/s. The gate count of our approach is 57% lower then the lookup table approach.
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